This invention relates to programmable logic integrated circuit devices, and more particularly to phase-locked loop ("PLL") circuitry for programmable logic devices.
It is well known to provide PLL circuitry on programmable logic devices for such purposes as counteracting clock signal propagation delay on the device, for enabling the device to convert from one clock signal frequency (e.g., an input clock signal frequency) to another different clock signal frequency (e.g., to be output by the device), etc. Some applications of programmable logic devices may require a PLL circuit to operate with frequencies outside a range that would be expected in most cases and for which a PLL circuit is readily designed. It would therefore be desirable to have PLL circuitry for programmable logic devices that can perform tasks conventionally requiring a PLL circuit to operate with very high and/or very low frequencies without the PLL circuitry that is provided having to support such a wide range of frequencies.
In view of the foregoing, it is an object of this invention to provide improved PLL circuitry for programmable logic devices.
It is a more particular object of this invention to provide PLL circuitry for programmable logic devices that extends the PLL capabilities of the devices without the necessity for extending the operating frequency range of any part of the PLL circuitry.